Critical Memory Accesses in Computer Architecture
|Critical Memory Accesses in Computer Architecture
|NAISS Small Compute
|Xiaoyue Chen <email@example.com>
|2024-01-31 – 2025-02-01
Data access speed is the major bottleneck for modern and emerging applications. Novel hardware architectures are needed to accelerate them. This project focuses on the critical memory accesses, i.e., the accesses that load data other load or branch instructions depend on. Different techniques will be experimented, including prefetching the critical loads, using a cache replacement policy that delays the evictions of the critical data. Simulation software such as Gem5 and ChampSim will be used to evaluate these techniques.