Improvements to a restricted out-of-order processor
Title: |
Improvements to a restricted out-of-order processor |
DNr: |
SNIC 2015/1-290 |
Project Type: |
SNIC Medium Compute |
Principal Investigator: |
Stefanos Kaxiras <stefanos.kaxiras@it.uu.se> |
Affiliation: |
Uppsala universitet |
Duration: |
2015-08-28 – 2016-09-01 |
Classification: |
10201 |
Homepage: |
http://www.it.uu.se/katalog/steka984 |
Keywords: |
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Abstract
In-order processors are very efficient at general purpose processing (W/MIPS) but unfortunately have very low performance. The Load Slice Core (LSC) microarchitecture has improved the performance of in-order cores by using them as a baseline, but by created a restricted out-of-order processor that optimizes the memory hierarchy instead of instruction-level parallelism (ILP). This work adepts to improve the LSC with a new forward-slicing technique and additional out-of-order techniques that provide high performance with high efficiency. This is an extension of our original Small project SNIC 2015/4-36 that, not that we are making progress, does not have enough allocated hours.